1. Field of the Invention
The present invention relates to programmable circuits. More specifically, the present invention relates to programmable circuits having an integrated architecture for programing and testing a programmable circuit.
2. Description of Related Art
Programmable logic devices (PLDs) are integrated circuits which are increasingly used to provide logic for electronic systems. These devices can implement user-defined logic functions by interconnecting user-configurable logic cells through a variety of semiconductor switching elements. The switching elements may be programmable elements such as fuses or antifuses which can be programmed to respectively connect or disconnect logical circuits. As it is well known, a fuse is a device having two electrodes and a conductive element which electrically connects the two electrodes. When a fuse is programmed, by passage of sufficient current between its electrodes, the two electrodes are electrically disconnected. By contrast, an antifuse is a structure, having two electrodes, which are not electrically connected when unprogrammed. However, when programmed the first and second electrodes of the antifuse are permanently electrically connected. An antifuse can be programmed by applying sufficient voltage ("programming voltage") between its first and second electrodes, thereby forming a bi-directional conductive link between the first and the second electrodes. Due to the relatively large size of currents required to program anti fuses, the current configuration of programming and testing circuitry, for programmable circuits utilizing antifuses, has several limitations.
FIG. 1 illustrates a programmable circuit 2 for programming and testing the circuitry of a Field Programmable Gate Array (FPGA) device. FPGAs are devices including arrays of programmable logic cells which can be interconnected by interconnect lines to generate complex functions which have multiple levels of logic. The interconnect lines of FPGAs typically include antifuses which can be programmed by coupling a high voltage to the antifuse to be programmed. In FIG. 1, supply pads 3 and 5 can be coupled to high voltage supplies Vpp1 and Vpp2. These supply pads are coupled to bus 12 which is routed around the chip to Shift Register Pumps (SRP) 4. The bus 12, in this particular example, is a two-line bus, having each of its lines connected to a different supply pad. The Shift Register Pumps are devices which can select a programmable line 14 and an antifuse 15 located on that routing line. The SRP 4 is also responsible for passing a large current through the anti fuse 15 thereby programming anti fuse 15. A multiplexing circuit 16, in this particular embodiment, selects either one of the supply voltages Vpp1, Vpp2, or Vss and couples the selected voltage to a programmable line 14. Generally to program an antifuse, a high voltage Vpp1 or Vpp2 is applied to one end 6 of the programmable line 14, and low voltage or ground is applied at the other end 8 of the programmable line 14, or vice versa. In theory, more than one programmable line could be coupled to the selected supply voltage Vpp. However, due to the large current required to program an anti fuse, in reality, only one programmable line is coupled to the supply voltage Vpp at one time. A more detailed discussion about the programming of antifuses can be found in U.S. Pat. No. 5,243,226 issued to Chan.
One problem with the circuit illustrated in FIG. 1 is that the input capacitance seen at the Vpp pads 3 and 5 is very large, approximately 40 pF. The input capacitance is very large because the Vpp pads 3 and 5 are directly coupled to the SRPs which have a very high capacitance. In the embodiment shown in FIG. 1, the bus 12 is routed over the entire chip to all the SRPs. Because the programming of antifuses requires high currents and voltages, the circuitry routed to the SRPs and the SRPs themselves have a very high capacitance. Since these Vpp pads are also utilized by users as input pins for accessing the input/output logic circuit 20, the large capacitance seen at the Vpp pads 3 and 5 directly interferes with the use of the input/output logic circuit 20.
Another problem with the circuit illustrated in FIG. 1 is related to test antifuses. Test antifuses 10 were inserted in each programmable line at both ends of each line to test the integrity of the programmable lines and of the SRPs. The integrity of a pump and of a programmable line could be tested by trying to blow the antifuse coupled, to the end of the line, remote from the respective SRP. However, by placing the test antifuses in the path of the programming current flowing through a programmable line, the amount of current flowing through the programmable line 14 would be reduced due to the impedance added by a test transistor coupled in parallel with the antifuse. Because the two additional test transistors coupled in parallel to the test antifuses would cause the impedance of the programmable line to increase, all the pass transistors coupled in parallel to the non-test antifuses had to be bigger to decrease the overall impedance of the programmable line such that a high enough programming current would flow through the programmable line. Consequently, the size of the conventional chip is affected by the larger non-test transistors required to compensate the increase in impedance caused by the test transistors.
Moreover, the test transistors required additional space on the chip due to the placement of these transistors in series with the programmable line. Furthermore, because test antifuses are coupled to the routing line that users utilize for connecting and accessing the logic on the chip the larger programming transistors, test antifuses, and test programming transistors add parasitic capacitance that negatively affects the performance of the chip.
Mother disadvantage of the circuit illustrated in FIG. 1 is that this circuit is limited to the programming of only two antifuses at one time. As explained above, to program antifuses, one needs to couple one Vpp pad to one end of the programmable line and ground or Vss to the other end of the programmable line. Because a large amount of current is required to program antifuses, one cannot program simultaneously more than one antifuse per programmable line. The circuit of FIG. 1 does not program more than one antifuse per SRP at one time, because it can only be connected to one VPP pad, or VSS. This causes the total programming time to be very high, considering that some chips have approximately 800,000 antifuses.
It is thus desirable to provide for a programmable circuit having an integrated programming and testing architecture which does not cause the input impedance seen by users to be very high. Additionally, it is desirable to provide an apparatus and method for programming programmable circuits wherein more than two programmable elements, such as an antifuse, can be programmed at one time. Also, it is desirable to provide an apparatus and method adapted to test programmable circuits wherein the test circuitry does not interfere with the projected size of the chip, the projected values of the programming current and voltage, the impedance of the routing line, or with the capacitance/performance of the routing lines.